The development cycle of a new computer system typically involves extensive empirical hardware verification and debugging of system timing problems. The need for such activity can be traced to various factors, including: the limited accuracy of software timing tools employed to predict performance of physical nets in the system and the effect of unmodeled phenomena (i.e., clock skew, cycle stealing, etc.). Taken together, these factors tend to create a difference between predicted system performance and empirically measured system performance. As a result, once a system is built there is a significant amount of activity to: (1) meet performance objectives with specified minimum manufacturing margins; and (2) exceed performance objectives with specified margins where time permits. This subsequent effort involves empirically discovering and improving performance limiting (i.e., critical) paths or improving paths that do not have sufficient manufacturing margin. In practice, the speed with which critical paths are isolated and modified is a significant consideration in the ultimate performance of a computer system to be shipped. Two factors which retard this effort are the state-of-the-art of timing failure diagnostics and the state-of-the-art of unlayering processing.
Timing failure diagnostics refers to the isolation of a failure to a specific chip (or net). Today, limited failure diagnostics is accomplished by stressing in common (e.g., delaying) computer system clocks. The stressing capabilities of current clock systems typically allows failure isolation down to a clock tree level. A clock tree, however, can have multiple outputs (e.g., twenty different outputs to twenty different chips). Thus, further isolation is typically required. Also, error checking logic will often not isolate a problem to a specific chip of the computer system.
Unlayering processing refers to an ability to temporarily work around a known timing failure to identify a next system failure. This is done by delaying (i.e., stressing) the capturing clock signal to the failing logic, which in turn allows the continuation of failure discovery without having to apply a "permanent fix" to a currently identified failure. The application of permanent fixes often involves modification of system hardware, which is obviously an expensive and time consuming process. Unlayering is employed to minimize the time required to fix failures by allowing multiple failures to be successively identified, and therefore corrected in parallel in hardware. Unfortunately, available clock tuning systems have limited unlayering capabilities since an entire tree must be delayed. Clock stressing of an entire tree often causes new problems because a clock tree typically feeds many chips in a system.
Thus, a new programmable clock tuning system and method with enhanced timing failure diagnostics and unlayering capabilities is desirable to reduce development time of new computer systems, particularly, such a system and method wherein individual clock signals may be separately shifted.